Generally, the semiconductor memory device is supplied with a power source voltage VDD and a ground voltage VSS from the outside and generates an internal voltage which is necessary for internal operations. As the voltage which is necessary for the internal operations of the semiconductor memory device, there are a core voltage VCORE supplied to a memory core region, a high voltage VPP used to drive a word line or during an overdriving, and a back bias voltage VBB supplied as a bulk voltage of NMOS transistor in the core region.
The level of various internal voltages can be subject to fluctuation due to a level change in the power source voltage VDD or a rapid consumption of the current, in which the fluctuation of the internal voltage acts as an obstacle factor against a high speed operation in a low power source voltage VDD. Therefore, in order to reduce the fluctuation of the internal voltage, the prior semiconductor memory device allows the internal voltage to be maintained stably using the reservoir capacitor array which can provide sufficient charge to the internal voltage.
FIG. 1 is a drawing showing the structure of the semiconductor memory device including the reservoir capacitor array according to prior art.
As shown in FIG. 1, the prior semiconductor memory device has various reservoir capacitor arrays for maintaining the internal voltage stably arranged in a peri region. As the reservoir capacitor array included in the prior semiconductor memory device, there are a peri voltage reservoir capacitor array for maintaining the peri voltage stably, a back-bias voltage reservoir capacitor array for maintaining the back-bias voltage stably, and a high voltage reservoir capacitor array for maintaining the high voltage VPP stably. Each of such various reservoir capacitor arrays is configured with a plurality of reservoir capacitors.
FIG. 2 is an equivalent circuit diagram of the reservoir capacitor included in the reservoir capacitor array according to prior art.
As shown in FIG. 2, the reservoir capacitor is consisted of capacitors C1, C2 connected in parallel between a power source voltage VDD and a ground voltage VSS. The capacitors are connected in parallel for the purpose of ensuring sufficient capacitance.
By the way, the capacitors C1, C2 included in the reservoir capacitors are subject to a defect or a physical damage during a manufacturing process and thus the leakage current through the capacitors C1, C2 can be generated. For example, if the physical damage is caused in the capacitor C1, the leakage current is generated through the capacitor C1. Since such generated leakage current can lead to an increase in current consumption at a standby state, it acts as a fatal obstacle factor in a mobile product in which the current consumption at the standby state is a substantial performance index.